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LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT
FPD1500SOT89
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PERFORMANCE (1850 MHz) 27.5 dBm Output Power (P1dB) 17 dB Small-Signal Gain (SSG) 1.2 dB Noise Figure 42 dBm Output IP3 50% Power-Added Efficiency Evaluation Boards Available Available in Lead Free Finish: FPD1500SOT89E DESCRIPTION AND APPLICATIONS The FPD1500SOT89 is a packaged depletion mode AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (pHEMT). It utilizes a 0.25 x 1500 m Schottky barrier Gate, defined by highresolution stepper-based photolithography. The recessed and offset Gate structure minimizes parasitics to optimize performance, with an epitaxial structure designed for improved linearity over a range of bias conditions and input power levels. The FPD1500 is available in die form and in other packages. Typical applications include drivers or output stages in PCS/Cellular base station highintercept-point LNAs, WLL and WLAN systems, and other types of wireless infrastructure systems.
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ELECTRICAL SPECIFICATIONS AT 22C
Parameter Power at 1dB Gain Compression Small-Signal Gain Power-Added Efficiency POUT = P1dB Noise Figure Output Third-Order Intercept Point (from 15 to 5 dB below P1dB) Saturated Drain-Source Current Maximum Drain-Source Current Transconductance Gate-Source Leakage Current Pinch-Off Voltage Gate-Source Breakdown Voltage Gate-Drain Breakdown Voltage IDSS IMAX GM IGSO |VP| |VBDGS| |VBDGD| NF IP3 VDS = 5.0V; IDS = 50% IDSS VDS = 5.0V; IDS = 50% IDSS Matched for best P1dB Matched for best IP3 at 50% IDSS VDS = 1.3 V; VGS = 0 V VDS = 1.3 V; VGS +1 V VDS = 1.3 V; VGS = 0 V VGS = -5 V VDS = 1.3 V; IDS = 1.5 mA IGS = 1.5 mA IGD = 1.5 mA 0.7 12 12 375 42 465 750 400 1 1.0 16 16 15 1.3 550 mA mA mS A V V V 38 1.2 40 dBm 1.5 dB Symbol P1dB SSG PAE Test Conditions VDS = 5.0V; IDS = 50% IDSS VDS = 5.0V; IDS = 50% IDSS VDS = 5.0V; IDS = 50% IDSS Min 26.0 15.5 Typ 27.5 17 50 Max Units dBm dB % RF SPECIFICATIONS MEASURED AT f = 1850 MHz USING CW SIGNAL
Phone: +1 408 850-5790 Fax: +1 408 850-5766
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Revised11/11/05 Email: sales@filcsi.com
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT
FPD1500SOT89
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ABSOLUTE MAXIMUM RATINGS1
Parameter Drain-Source Voltage Gate-Source Voltage Drain-Source Current Gate Current RF Input Power
2
Symbol VDS VGS IDS IG PIN TCH TSTG PTOT Comp.
3 2
Test Conditions -3V < VGS < +0V 0V < VDS < +8V For VDS > 2V Forward or reverse current Under any acceptable bias state Under any acceptable bias state Non-Operating Storage See De-Rating Note below Under any bias conditions 2 or more Max. Limits
Min
Max 8 -3 IDSS 15 350 175
Units V V mA mA mW C C W dB %
Channel Operating Temperature Storage Temperature Total Power Dissipation Gain Compression Simultaneous Combination of Limits
1 3
-40
150 2.3 5 80
TAmbient = 22C unless otherwise noted Max. RF Input Limit must be further limited if input VSWR > 2.5:1 Users should avoid exceeding 80% of 2 or more Limits simultaneously
Notes: * Operating conditions that exceed the Absolute Maximum Ratings will result in permanent damage to the device. * Total Power Dissipation defined as: PTOT (PDC + PIN) - POUT, where: PDC: DC Bias Power PIN: RF Input Power POUT: RF Output Power * Total Power Dissipation to be de-rated as follows above 22C: PTOT= 2.3W - (0.015W/C) x TPACK where TPACK = source tab lead temperature above 22C (coefficient of de-rating formula is the Thermal Conductivity) Example: For a 65C source lead temperature: PTOT = 2.3W - (0.015 x (65 - 22)) = 1.66W
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HANDLING PRECAUTIONS To avoid damage to the devices care should be exercised during handling. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. These devices should be treated as Class 1A per ESD-STM5.1-1998, Human Body Model. Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263. APPLICATIONS NOTES & DESIGN DATA Applications Notes are available from your local Filtronic Sales Representative or directly from the factory. Complete design data, including S-parameters, noise data, and large-signal models are available on the Filtronic web site. Evaluation Boards available upon request.
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Phone: +1 408 850-5790 Fax: +1 408 850-5766
http://www.filtronic.co.uk/semis
Revised11/11/05 Email: sales@filcsi.com
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT
FPD1500SOT89
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BIASING GUIDELINES Active bias circuits provide good performance stabilization over variations of operating temperature, but require a larger number of components compared to self-bias or dual-biased. Such circuits should include provisions to ensure that Gate bias is applied before Drain bias, otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for additional information. Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage supply for depletion-mode devices such as the FPD1500SOT89. Self-biased circuits employ an RF-bypassed Source resistor to provide the negative Gate-Source bias voltage, and such circuits provide some temperature stabilization for the device. A nominal value for circuit development is 2.6 for a 50% of IDSS operating point. For standard Class A operation, a 50% of IDSS bias point is recommended. A small amount of RF gain expansion prior to the onset of compression is normal for this operating point. Note that pHEMTs, since they are "quasi- E/D mode" devices, exhibit Class AB traits when operated at 50% of IDSS. To achieve a larger separation between P1dB and IP3, an operating point in the 25% to 33% of IDSS range is suggested. Such Class AB operation will not degrade the IP3 performance. PACKAGE OUTLINE
(dimensions in mm)
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PCB Foot Print
Units in inches
All information and specifications subject to change without notice.
Phone: +1 408 850-5790 Fax: +1 408 850-5766
http://www.filtronic.co.uk/semis
Revised11/11/05 Email: sales@filcsi.com
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT * TYPICAL TUNED RF PERFORMANCE
FPD1500SOT89
Power Transfer Characteristic
3.50 29.00
Pout Comp Point
3.00 2.50
27.00 25.00
Output Power (dBm)
23.00 21.00 19.00 17.00 15.00 13.00 -2.00
2.00 1.50 1.00 .50 .00 -.50 16.00
0.00
2.00
4.00
6.00
8.00
10.00
12.00
14.00
Input Power (dBm)
Drain Efficiency and PAE
70.00%
70.00%
60.00%
PAE Eff.
60.00%
50.00% PAE (%)
50.00%
Drain Efficiency (%)
40.00%
40.00%
30.00%
30.00%
20.00%
20.00%
10.00%
10.00%
.00% -2.00
0.00
2.00
4.00
6.00
8.00
10.00
12.00
14.00
.00% 16.00
Input Power (dBm)
Typical power, efficiency, and intermodulation performance is shown above. The devices were biased nominally at VDS = 5V, IDS = 50% of IDSS, at a test frequency of 2 GHz. The test devices were tuned (input and output tuning) for maximum output power at 1dB gain compression.
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Gain Compression (dB)
Revised11/11/05 Email: sales@filcsi.com
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT
FPD1500SOT89
Typical Intermodulation Performance VDS = 5V IDS = 50% IDSS at f = 1.85GHz
-10.00 25.00 -15.00 -20.00 23.00
-25.00 -30.00 -35.00 19.00 -40.00 -45.00 17.00 -50.00 15.00 -1.00 1.00 3.00 5.00
Input Power (dBm)
21.00
-55.00 7.00 9.00 Pout 11.00 Im3, dBc
Note: pHEMT devices exhibit non-classical intermodulation performance, with equivalent IPvalues exceeding 14 dB above P1dB. This IMD enhancement is affected by the quiescent bias current, the Drain-Source voltage, and the tuning or matching applied to the device. Maximum Stable Gain & S21
FPD1500SOT89 5V / 50%IDSS
35 30
MSG S21
MSG
25 20 15 10 5 0 0.5 1.5 2.5 3.5 4.5 5.5 Frequency (GHz) 6.5 7.5 8
Mag S21
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3rd Oder IM Poroducts (dBc)
Output Power (dBm)
Revised11/11/05 Email: sales@filcsi.com
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT * TYPICAL OUTPUT PLANE POWER CONTOURS (VDS = 5V, IDS = 50% IDSS)
FPD1500SOT89
0. 6 0.4
0. 8
1. 0 2. 0
Swp Max 159
3.0
22dBm
0.2
4.0 5.0
23dBm 24dBm
0 0. 2 0. 26dBm 0. 6 4 0. 1. 8 0 2. 0 3. 4. 5. 0 00
10.0 10 .0
25dBm
27dBm
-0.2
-10.0
28dBm
-5.0 -4.0 -3.0 -0.4 0. 6 2. 0 1. 0
1850 MHz Contours swept with a constant input power, set so that nominal P1dB is achieved at the point of optimum output match. Input (Source plane) s: 0.74 168.2 0.15 + j0.1 (normalized) 7.5 + j5.0 Nominal IP3 performance is obtained with this input plane match, and the output plane match as shown.
0. 8
Swp Min 1
0. 6 0.4
0. 8
1. 0 2. 0
Swp Max 123
3.0
0.2
23dBm 24dBm 25dBm 26dBm
0. 2 0. 27dBm 4 0. 6 0. 1. 0 8 2. 0 3. 4. 5. 0 00
4.0 5.0
10.0 10 .0
0
28dBm
-10.0 -0.2 -5.0 -4.0 -0.4 0. 6
22dBm
2. 0 1. 0
-3.0
900 MHz Contours swept with a constant input power, set so that nominal P1dB is achieved at the point of optimum output match. Input (Source plane) s: 0.67 103.6 0.30 + j0.74 (normalized) 15 + j37.0 Nominal IP3 performance is obtained with this input plane match, and the output plane match as shown.
0. 8
Swp Min 1
Phone: +1 408 850-5790 Fax: +1 408 850-5766
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Revised11/11/05 Email: sales@filcsi.com
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT * TYPICAL SCATTERING PARAMETERS (50 SYSTEM)
FPD1500SOT89
See Website "More Info" for S-parameter design files.
FPD1500SOT89 5V / 50%IDSS
1.0
6 0.
4 GHz
2. 0
5 GHz
6 GHz 7 GHz
Swp Max 8GHz
0.8
0. 4
3.5 GHz 3 GHz
0.2
3.
0
0 4.
5.0
2.5 GHz
10.0 0.2 0.4 0.6 0.8 1.0 2.0 3.0 4.0 5.0
10.0
0
2 GHz
1.52GHz
-4 .0 -5. 0
-0.
.41 -0
GHz
-0 .6
-2 .0
-0.8
FPD1500SOT89 5V / 50%IDSS
0. 8 0. 6 0.4 3.0 1. 0 2. 0
-1.0
S11
Swp Min 0.5GHz
Swp Max 8GHz
0.2
5 GHz 4 GHz 3 GHz
6 GHz
4.0
7 GHz
5.0
10.0 0. 0. 8 1. 0 2. 0 3. 4. 5. 0 00 10 .0
0
0. 2
2 GHz 6 4
0.
1 GHz
-10.0 -0.2 -5.0 -4.0 -0.4 0. 6 2. 0 1. 0 -3.0
S22
0. 8
Swp Min 0.5GHz
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-10.0
-3 .0
Revised11/11/05 Email: sales@filcsi.com
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT * TYPICAL I-V CHARACTERISTICS
DC IV Curves FPD1500SOT89 0.60
FPD1500SOT89
0.50
Drain-Source Current (A)
0.40
0.30
0.20
VG=-1.5V VG-1.25V VG=-1.00V VG=-0.75V VG=-0.5V VG=-0.25V VG=0V
0.10
0.00 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Drain-Source Voltage (V)
Note: The recommended method for measuring IDSS, or any particular IDS, is to set the Drain-Source voltage (VDS) at 1.3V. This measurement point avoids the onset of spurious self-oscillation which would normally distort the current measurement (this effect has been filtered from the I-V curves presented above). Setting the VDS > 1.3V will generally cause errors in the current measurements, even in stabilized circuits. Recommendation: Traditionally a device's IDSS rating (IDS at VGS = 0V) was used as a predictor of RF power, and for MESFETs there is a correlation between IDSS and P1dB (power at 1dB gain compression). For pHEMTs it can be shown that there is no meaningful statistical correlation between IDSS and P1dB; specifically a linear regression analysis shows r2 < 0.7, and the regression fails the F-statistic test. IDSS is sometimes useful as a guide to circuit tuning, since the S22 does vary with the quiescent operating point IDS.
Phone: +1 408 850-5790 Fax: +1 408 850-5766
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Revised11/11/05 Email: sales@filcsi.com
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT
* REFERENCE DESIGNS (0.9 & 1.85GHZ)
FPD1500SOT89
Frequency Gain P1dB IP3 S11 S22 Vd Vg Id
GHz dB dBm dBm dB dB V V mA
0.9 1.85 20 16 27 27 38 40 -5 -9 -15 -14 5 5 -0.4 to -0.6 -0.4 to -0.6 200 200
Component Values Component Lg Ld L1 L2 C1 0.9GHz 47nH 47nH 12nH 4.7nH 5.6pF 1.85GHz 27nH 27nH 1.5nH 4.7nH 2.2pF
Eval board material - 31mil thick FR4 with 1/2 Ounce Cu on both sides
Negative gate voltage required to be established before drain bias Use test clips at the bias vias at the top and bottom of the board for biasing
Eval Board Layout
Vg 33pF 0.01uF 20O Lg 33pF L1 33pF 0.01uF Vd
+ 1.0uF +
Q1
Ld C1 33pF
L2
Eval board Schematic
DCVS ID=V2 V=-0.5 V RES ID=R1 R=20 Ohm CAP ID=C6 C=33 pF IND ID=L2 L=Ld nH MLIN ID=TL13 W=35 mil L=95 mil MLIN ID=TL11 W=10 mil L=30 mil MLIN ID=TL7 W=73 mil L=60 mil
1 1
DCVS ID=V1 V=5 V
CAP ID=C5 C=33 pF
IND ID=L4 L=Lg nH
MLIN ID=TL4 W=10 mil L=30 mil MLIN ID=TL2 W=73 mil L=60 mil
1 2
MLIN ID=TL6 W=35 mil L=153 mil
CAP ID=C2 C=33 pF PORT P=1 Z=50 Ohm
MLIN ID=TL9 W=98 mil L=105 mil
3 2
IND ID=L3 L=L1 nH
2
MTEE ID=TL1 W1=98 mil W2=98 mil W3=105 mil
1 2 3
CAP ID=C1 C=33 pF PORT P=2 Z=50 Ohm
3
MTEE ID=TL12 W1=98 mil W2=98 mil W3=40 mil
MTEE ID=TL5 W1=98 mil W2=98 mil W3=40 mil
CAP ID=C4 C=C1 pF
SUBCKT ID=S1 NET="FPD1500SOT89"
IND ID=L1 L=L2 nH
Phone: +1 408 850-5790 Fax: +1 408 850-5766
http://www.filtronic.co.uk/semis
Revised11/11/05 Email: sales@filcsi.com
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT
* REFERENCE DESIGNS (2.4 & 2.6GHZ)
FPD1500SOT89
Component Values Component Lg Ld L1 L2 C1 C2 2.4GHz 22nH 22nH 1.0nH 3.3nH 1.8pF 1.0pF 2.6GHz 18nH 18nH Tab 3.9nH 1.0pF 1.0pF
Frequency Gain P1dB IP3 S11 S22 Vd Vg Id
GHz dB dBm dBm dB dB V V mA
2.4 2.6 12 11.5 28 27.5 41 40 -6 -16 -5 -5 5 5 -0.4 to -0.6 -0.4 to -0.6 200 200
Eval board material - 31mil thick FR4 with 1/2 Ounce Cu on both sides
Negative gate voltage required to be established before drain bias Use test clips at the bias vias at the top and bottom of the board for biasing
Eval Board Layout
Vg 33pF 0.01uF 20O Lg 33pF C1
L1
Vd 33pF 0.01uF Ld C2 33pF L2
+ 1.0uF +
Q1
Eval board Schematic
DCVS ID=V2 V=-0.5 V RES ID=R1 R=20 Ohm CAP ID=C6 C=33 pF IND ID=L2 L=Ld nH MLIN ID=TL13 W=35 mil L=95 mil MLIN ID=TL11 W=10 mil L=30 mil MLIN ID=TL7 W=73 mil L=60 mil
1 1
DCVS ID=V1 V=5 V
CAP ID=C5 C=33 pF
IND ID=L4 L=Lg nH
MLIN ID=TL4 W=10 mil L=30 mil MLIN ID=TL2 W=73 mil L=60 mil
1 2
MLIN ID=TL6 W=35 mil L=153 mil
CAP ID=C2 C=33 pF PORT P=1 Z=50 Ohm
MTEE ID=TL3 W1=98 mil W2=98 mil W3=105 mil
1 3 2
3 2
IND ID=L3 L=L1 nH
2
MTEE ID=TL1 W1=98 mil W2=98 mil W3=105 mil
1 2 3
CAP ID=C1 C=33 pF PORT P=2 Z=50 Ohm
3
CAP ID=C3 C=C1 pF
MTEE ID=TL12 W1=98 mil W2=98 mil W3=40 mil
MTEE ID=TL5 W1=98 mil W2=98 mil W3=40 mil
CAP ID=C4 C=C2 pF
SUBCKT ID=S1 NET="FPD1500SOT89"
IND ID=L1 L=L2 nH
Phone: +1 408 850-5790 Fax: +1 408 850-5766
http://www.filtronic.co.uk/semis
Revised11/11/05 Email: sales@filcsi.com
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT
FPD1500SOT89
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STATISTICAL SAMPLE OF RF PERFORMANCE
Small Signal Gain
6000
Noise Figure
14000 12000 10000 8000 6000 4000 2000 0 13 14 15 16 17 Gain (dB) 18
5000 4000 Count 3000 2000 1000 0 0.6 0.7 0.8 0.9 1 1.1 1.2 NF (dB) 1.3
Count
Output Power at 1dB Gain Compression
14000 12000 10000 Count 8000 6000 4000 2000 0 23 24 25 26 27 P1dB (dBm) 28 Count 6000 5000 4000 3000 2000 1000 0 30
Output 3 -Order Intercept Point
rd
32
34
36
38
40
42
44
IP3 (dBm)
The histograms above represent a sample of over 20,000 representative devices. The devices were tested by a high-speed automatic test system, in a matched circuit based on the EB1500SOT89AA Evaluation Board design (see the Website for a schematic). This circuit is a dual-bias single-pole lowpass topology, and the devices were biased at VDS = 4.5V, IDS = 120mA. The performance data is summarized below:
Parameter Median Standard Deviation 0.20 0.03 0.25 1.1 Test Limit CPK
Small-Signal Gain Noise Figure Output Power (P1dB) 3rd-Order Intercept
15.5 0.91 25.2 38.7
14.5 1.20 24.5 36.5
1.7 3.2 0.93 0.67
Phone: +1 408 850-5790 Fax: +1 408 850-5766
http://www.filtronic.co.uk/semis
Revised11/11/05 Email: sales@filcsi.com

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